I can say I am more of an RTL design engineer. I had a lot of experience in RTL design deployed in FPGA systems before gaining interest in IC design. In FPGA, or now also in SoC (Processing System [PS] + Programmable Logic [PL]) you write your RTL code in one of the HDLs, namely […]
Etiket: FPGA
Is it Worth to Design a RISC-V Core from Scratch?
I don’t think there is anyone who never heard about RISC-V in the year of 2023, who works in the area of embedded systems or digital design and verification. If you never heard about it, please look at RISCV international webpage: https://riscv.org/ RISC-V is a royalty-free, open-standard instruction set architecture (ISA). Well, if you never […]
Verification of a Custom AXI-Stream IP with VHDL using UVVM Library
In my latest post, I showed how to create a custom AXI-Stream IP in Vivado. This basic IP was an arithmetic coprocessor accelerator, performs addition, subtraction or multiplication according to the configuration: https://www.mehmetburakaykenar.com/creating-custom-axi-stream-ip-tutorial-with-vivado/397/ In that post, I just showed how to create the IP in Vivado and write the RTL code, but did not verify […]
Creating Custom AXI-Stream IP Tutorial with Vivado
In my latest post, I talked about AXI-Stream protocol and showed a running design on Zedboard utilizing AXI-Stream FIFO and ILA: https://www.mehmetburakaykenar.com/what-is-axi-stream-protocol-axi-stream-fifo-tutorial-with-vivado-and-vitis-running-on-zynq-zedboard/377/ Today, I will show how to create a custom AXI-Stream peripheral in Vivado with VHDL. The use case is an arithmetic co-processor, where the arithmetic operation of the co-processor will be selected between […]
What is AXI-Stream protocol? AXI-Stream FIFO Tutorial with Vivado and Vitis, running on ZYNQ, ZEDBOARD
So far in my blogs I utilized Zynq PS DMA and AXI CDMA IPs to move data between DDR RAM, on-chip ram (OCM) and PL Block RAM (BRAM). I have designed Vivado HW and Vitis SW parts and showed latency results for these two scenarios, which you can find at the links all the details: […]
XILINX ZYNQ AXI Central DMA (CDMA) On-Chip Memory (OCM), DDR3 RAM and PL Block RAM Data Transfer Performances
It has been a long time that I posted on my webpage related to Digital Design and SoC concepts. My last post was related to evaluating data transfer rates between OCM, DDR3 RAM and PL Block RAM by utilizing PS DMA of Processing System of the Zynq SoC. Please visit the related post for details: […]
XILINX ZYNQ PS DMA | On-Chip Memory (OCM), DDR3 RAM and PL BRAM Data Transfer Performances
It has been a long time that I posted on my webpage related to Digital Design and SoC concepts. This post will be related to Zynq Processing System (PS) DMA usage example and performance analysis on data transfer between DDR3 RAM, OCM and PL Block RAM. I will provide both PL and PS designs and […]
Synthesis N-bit Counter with Open-Source Yosys Synthesizer
In this post, I will show how to install Yosys open source synthesizer and how to use basiccommands. Also I will synthesize N-bit counter that I have written in the first post of this series. Yosys works on Linux environment. If you are a Windows user and want to use Yosys, you needCygwin to emulate […]
FPGA Synthesis | Xilinx Spartan-3E/6 and 7-Series Library Analysis
In my previous, actually first post about ASIC design with open source tools, I talked about the first automation step, which is synthesis and its output, which is a netlist: https://www.mehmetburakaykenar.com/first-step-to-asic-design-synthesis-netlist-verilog-counter-example-on-vivado/254/ We saw that an N-bit Verilog counter code is synthesized into logic cells and nets connecting them. File formats for this information in Vivado […]
First Step to ASIC Design: Synthesis & Netlist | Verilog Counter Example on Vivado
This is the first post on this subject: Open Source ASIC Design. I am interested in ASIC design recently. For years (>10) I designed digital circuits with VHDL. At the beginning of this year (2022), I started working in Yongatek Microelectronics company, located in Istanbul and Ankara in Turkey. Here WE {I adapted quickly and […]