I can say I am more of an RTL design engineer. I had a lot of experience in RTL design deployed in FPGA systems before gaining interest in IC design. In FPGA, or now also in SoC (Processing System [PS] + Programmable Logic [PL]) you write your RTL code in one of the HDLs, namely Verilog/VHDL/SV, or maybe in higher level platforms and languages which they can generate HDL, then synthesize, P&R and generate bitstream in the flow. There are a few FPGA companies and they also provide their EDA tools, which you can design and run the flow. AMD Vivado and Intel Quartus are one of the most popular EDA tools for HDL design flow. Most of the times tools are GUI based and easy for user experience. Of course there are script way methodologies to run the flow without opening any kind of GUI such as Vivado Non-Project mode, mostly utilized with TCL scripting. But, a lot FPGA users stick with GUI approach. Therefore, most of the time, it is not a big obstacle for engineers to learn and use FPGA EDA tools, where there are tons of written or video tutorials freely available on the web. Almost all FPGA vendors provide free versions of their EDA tools, in which you can download and work on. For small capacity FPGAs, FPGA vendors don’t want any license, so it is easy for students and hobbyists also to work on FPGA based systems.
IC design field has different components: RTL design, verification, physical design etc. and these steps have a very similar approach with FPGA design. There are 3 EDA tool providers for complete IC design flow: Cadence, Synopsys and Siemens, while Cadence and Synopsys seem to have more share in the market than Siemens. However, when you google IC design tutorials or EDA tools to have a look at, now the challenge starts! You can’t see any kind of detailed documentation or video tutorials on these devices or you can’t simply download an installation package like you normally do in FPGA EDA tools. If you are not familiar with IC design EDA tools, they mostly run on Linux servers and you need a remote connection to work on them, while most of the times it can be challenging to get a license if multiple engineers want to work on same tool. By the way, having an IC design license not something you buy just to work around and try tutorials, they are far more expensive than any license you have to buy for FPGA programming, and also they are time-limited.
So the question arises, how to learn IC design as a student, as a hobbyist or an engineer who wants to try IC design? Well if you are at university, some universities can provide IC design EDA tool licenses to students with their agreements to the companies, if you are lucky! For example in Turkiye, not every university can provide these licenses. So, most electronics engineering departments can not provide IC design or VLSI design courses due to lack of EDA licenses or capable academic staff. This unpromising situation slowly getting to a level such that any student in any university now can download an IC design EDA tool, work on it, generate production ready ICs freely. Bonus tip: These tools and production libraries (Standard Logic Cell Libraries) are opensource! So, one can also go trough how EDA tools work in each step, even try different algorithms in these stages.
In this post, I want to show a full IC design flow from how to download the EDA tool, build it, then design and generate a GDSII output for a RISC-V core as a macro, which can simply defined as a black-box IP that you can integrate it into your designs such as in an MCU or SoC. The open-source tool that we will generate our macro IPs GDSII output will be “Openlane” from OpenROAD. I don’t want to get into details of what are open-source tools and will jump directly into the tutorial. These are the links for OpenROAD and Openlane. I strongly suggest to look at and read theme thoroughly if you never heard what are those.
https://github.com/The-OpenROAD-Project/OpenROAD
https://github.com/The-OpenROAD-Project/OpenLane
However, I will copy what is written in README of the OpenROAD just to give insight about the project:
OpenROAD eliminates the barriers of cost, schedule risk and uncertainty in hardware design to promote open access to rapid, low-cost IC design software and expertise and system innovation. The OpenROAD application enables flexible flow control through an API with bindings in Tcl and Python.
OpenROAD is used in research and commercial applications such as,
OpenROAD-flow-scripts from OpenROAD
OpenLane from Efabless
Silicon Compiler from Zero ASIC
Hammer from UC Berkeley
OpenFASoC from IDEA-FASoC for mixed-signal design flows
OpenROAD fosters a vibrant ecosystem of users through active collaboration and partnership through software development and key alliances. Our growing user community includes hardware designers, software engineers, industry collaborators, VLSI enthusiasts, students and researchers.
OpenROAD strongly advocates and enables IC design-based education and workforce development initiatives through training content and courses across several global universities, the GoogleSkyWater shuttles also includes GlobalFoundries shuttles, design contests and IC design workshops. The OpenROAD flow has been successfully used to date in over 600 silicon-read tapeouts for technologies up to 12nm.
Openlane has a very good documentation and it’s getting better each and every day:
https://openlane.readthedocs.io/en/latest/
In this documentation, you can find information about cloning and installing Openlane, just check the document. I am using Ubuntu 20.04 and I simply followed this documentation the install Openlane in Ubuntu. If you have necessary packages are installed, then it is just running a makefile to install and test the installation:
git clone --depth 1 https://github.com/The-OpenROAD-Project/OpenLane.git
cd OpenLane/
make
make test
If everything is OK, then now we have all the tools, both for EDA and standard logic cell library of SKY130 nm.
Now, in an IC design, you will utilize and integrate into your design a lot of IPs, which have already been hardened. A CPU core is one of a such IPs you can buy in designing an MCU or SoC. RISC-V is now very popular among CPU cores, due to it’s flexibility and not having license or royalty. But, of course this is the case if you design your own RISC-V core, or use an open-source one. In this post, I will use a very famous open-source RISC-V core implementation, PicoRV32:
https://github.com/YosysHQ/picorv32
PicoRV32 core different configuration options, which can be configured via Verilog parameters. I want to continue after this post integrating the RISC-V core into a simple SoC. In PicoRV32 repo, there is also an example SoC implementation which utilizes PicoRV32 core. So, I will configure our RISC-V core according the configuration utilized in this SoC. I needed to make simple modifications in the Verilog file of the core. First, I created independent Verilog files that are included in picorv32.v file in the repo. Then, I edited ports section of the module to adapt SoC integration. I also needed to add power pins, namely vccd1 and vssd1 for power connections to the macro. You can check RTL files used to generate the macro GDS in my github repo:
https://github.com/mbaykenar/apis_anatolia/tree/main/OPEN_SOURCE_ASIC_DESIGN/rtl
In Openlane default directory tree, there is a folder named “designs”. I created a new folder in it and named it as “picorv32”. I added my RTL and SDC constraint files into a new folder called “src”. I also created a config.tcl file and a pin_order.cfg file. I also uploaded these files into same repo that I shared the link.
In order to generate GDS output for a macro IP, we need a configuration file, which has the information and directives for the IC design steps, such as synthesis, floorplan, placement, CTS, routing and other steps. We need another file for pin information, such as in which edge of the macro these which pins reside. Of course we need RTL files, only Verilog in Openlane, which reside in src folder.
After arranging these files in designs directory, actually it is just running the flow.tcl script in docker image with this command:
> make mount
> ./flow.tcl -design picorv32Well, it is not that easy! Most of the times, you need to run numerous times the flow to get an optimum area and performance results, also an error-free design. I will show some of the errors that I had during the flow and their solutions.
I first got an error in STEP 4 -> IO Placement
I checked the pin_order.cfg file and saw that I missed some ports in the module to add in this file. I added missing ports and the error has gone.
Then I got an error in STEP 23 -> Detailed Routing
This error happened as the tool could not finish connecting all the nets. I checked config.tcl file and realized that I forgot to increase DRT_OPT_ITERS parameter. This parameter is 64 by default, however I usually start the flow with a small number to see if routing steps are going to converge or not. I increased this parameter to 20 and router finally finished connection all the nets.
Then I got an error in STEP 31 -> IR Drop Report
In order to solve this problem, I first disabled IR DROP with setting RUN_IRDROP_REPORT to 0. It removed the error, you won’t have IR DROP analysis though. Then I added set ::env(RT_MAX_LAYER) “met4” parameter and then the problem solved, also now I got IR DROP analysis.
Then I got another error in STEP 32 -> GDS Klayout
I even opened an issue in Openlane repo about this error. But then, I solved the problem by only using vccd1 and vssd1 for power nets.
https://github.com/The-OpenROAD-Project/OpenLane/issues/2079
Don’t forget, there are different configuration options when targeting macro hardening and chip top module. In macro hardening, you need to use these parameters below:
set ::env(FP_PDN_CORE_RING) 0
set ::env(FP_PDN_MULTILAYER) 0
set ::env(RT_MAX_LAYER) "met4"
You need to check Openlane documentation and github repo to understand better the configuration options.
After all those, if you are lucky enough, you can see the green text “[SUCCESS]: Flow complete.”.
In runs/RUN_YEAR.MM.DD_HH.MM.SS/results/signoff/ directory, you can find picorv32.gds file
and open it with Klayout.
I added some views from Klayout here. Full layers, metal1, metal2, metal3 and metal4
connections:
All layers:
met1 layer:
met2 layer
met3 layer:
met4 layer:
In this post, I briefly talked about how to harden a macro for an open-source RISC-V CPU core, namely PicoRV32 in an open-source IC design EDA tool, namely Openlane. I plan to prepare how to use this IP macro in an SoC in the next post.
You can find Openlane related files in my github repo:
https://github.com/mbaykenar/openlane-designs
Regards,
Mehmet Burak AYKENAR
You can connect me via LinkedIn: Just sent me an invitation
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