In the previous post, I was able to harden a RISC-V based SoC in Openlane. There were 3 methods to harden the chip according to Efabless documentation and I utilized the first method, which was hardening the macros first, then integrating all the macros in the top module by instantiating them, while there must be […]
Etiket: ASIC
RISC-V Based SoC Design with Open-Source Openlane IC Design Tool
This is the second post for the series of open-source IC design flow. The first post talked about how to use open-source tools, namely Openlane to harden a RISC-V CPU core, in which we generated GDS outputs of the CPU core. The famous PicoRV32 RISC-V core is chosen for this purpose. You can find the […]
Open-Source IC Design Flow for an Open-Source RISC-V Core
I can say I am more of an RTL design engineer. I had a lot of experience in RTL design deployed in FPGA systems before gaining interest in IC design. In FPGA, or now also in SoC (Processing System [PS] + Programmable Logic [PL]) you write your RTL code in one of the HDLs, namely […]
First Step to ASIC Design: Synthesis & Netlist | Verilog Counter Example on Vivado
This is the first post on this subject: Open Source ASIC Design. I am interested in ASIC design recently. For years (>10) I designed digital circuits with VHDL. At the beginning of this year (2022), I started working in Yongatek Microelectronics company, located in Istanbul and Ankara in Turkey. Here WE {I adapted quickly and […]