Is it Worth to Design a RISC-V Core from Scratch?

I don’t think there is anyone who never heard about RISC-V in the year of 2023, who works in the area of embedded systems or digital design and verification. If you never heard about it, please look at RISCV international webpage:

RISC-V is a royalty-free, open-standard instruction set architecture (ISA). Well, if you never heard RISCV, at least you have to know about ARM. ARM is very famous in embedded system world, even maybe we can say ARM is everywhere! I don’t have the exact numbers, but I got this figure from “statistica”:

So, it seems on average 7-8 billion chips having ARM IPs are shipped for every quarter. Another news from 2021 claims that 900 ARM-based chips are shipping for every second, 70 million per day:

But, ARM ISA is licensed to ARM and you first have to pay a licensing fee to use their CPU core and other IPs before any shipment. Later, when you produce your chip, you also have to pay a “royalty fee” to ARM per each IC. The royalty fee is around %1-%2 according to some data from the web:,selling%20price%20of%20the%20chip

For example, if you sell your IC 10$, then you have to pay 0.1$ to ARM for each IC you sell. If you sell 10 million ICs, you have to pay 1 Million $ to ARM in total. In the link above, they estimated %50 percent of ARM’s revenue comes from “royalty fees”.

RISC-V ISA is “royalty-free”, which means, you can design (or buy from a RISC-V core IP provider) a RISC-V ISA compatible CPU and use it in your SoC without any extra payment for selling each of your ICs.

Are RISC-V cores free? Of course not! There are dozens of companies who design and sell RISC-V cores. Here you can find some of them:






Remember, RISC-V is a royalty-free ISA, so you don’t have to go one of the RISC-V CPU core IP providers and pay them, you can build one yourself, or even there are dozens of open-source RISC-V IPs, why not using them?

Let’s consider the first choice, building a RISC-V CPU core by yourself. Well, you need some computer architecture specialists, some RTL designers and verification engineers. They can design a RISC-V core and verify it and then you can use this core in your SoC, instead of buying a core from the IP providers.

However, this approach is not very practical since probably you will spend more money than buying an IP, and also you will lose time, which is most critical in a very competitive environment.

The second option seems more promising, at least this time you don’t need to hire computer architecture and RTL engineers, but you will still need verification engineers, if you are not that crazy to use an open-source project in a commercial product without verifying it. There are tons of open-source RISC-V cores with different specialties and from day to day the number is increasing. But, then a problem arises, which open-source cpu core to choose? Here are some very famous and most starred github repos of open-source RISC-V CPU cores:








Some of these cores gained special interest from the industry and found them being used in commercial products, possibly with some minor modifications. One of the most popular open-source RISC-V cores is VexRiscv. This core was the winner in RISC-V organization’s “SoftCPU Contest”:

Efinix, one of the FPGA vendors, has 3 different SoC implementations in their FPGAs, all of them are based on VexRiscv:

cv32e40p is another RISC-V ISA CPU core, which is maintained by OpenHW Group. The importance of cv32e40p is that it is utilized in core-v-mcu project, again maintained by OpenHW Group and as of 2023 they taped-out this mcu for a development kit:

ibex from LowRISC is another famous open-source RISC-V CPU core, which is utilized in a lot of both open-source and commercial SoC products.

ibex and cv32e40p were originally from ETH Zurich’s PULP team. In PULP website, there is a page called “PULP Users”, where companies and organizations using PULP cores in their projects are listed:

After all these information, I want to return the question, which is the title of this post: Is it worth to design a RISC-V core from scratch? As far as I know, most companies who uses RISC-V cores in their SoCs or other products, buy an available IP from IP providers or take one of the famous and well maintained open-source RISC-V cores and integrate it into their system, instead of designing a RISC-V core by themselves. One reason for this decision, there are a number of maintainers in some open-source projects such as ibex or cv32e40p, since they are maintained by professional foundations or organizations such as OpenHW Group and LowRISC. Numerous contributors around the world use, extend or debug these cores. But, this is a commercial and economic perspective. What about educational perspective?

In my opinion, learning by doing is a crucial step in the learning path of a concept. Of course, reading manuals or datasheets, specifications, textbooks, looking into source codes if it is an open-source project, watching videos related to the subject are very important to learn a subject. But, in engineering, especially computer and electronics, you get a comprehensive understanding of the subject when you do it by yourself, if possible of course. I mean, if you want to learn how digital filters work, of course you first go to famous Oppenheim book, or videos related to the subject. But, when you try to “build” an FIR filter with certain cutoff frequency, passband ripple and stopband attenuation requirements in MATLAB or Python for example, you force yourself and learn a lot of things on the way. Building a RISC-V CPU core has also the same effect.

Most universities give the assignment of a CPU design in HDL, in their computer architecture courses. After RISC-V gained attention, universities from day to day started to teach RISC-V in their curriculum. I also taught a one semester computer architecture course as a part-time lecturer and chose RISC-V as an example ISA. I gave as a semester project a simple 16-bit CPU design with a very limited instruction set. Students who designs a CPU will learn a lot more than others who don’t. Even, in Turkiye, we have a RISC-V CPU design competition in Teknofest “TEKNOFEST AEROSPACE AND TECHNOLOGY FESTIVAL”, which this CPU design contest will be held in 3rd time in 2024. Here is the specification for the latest contest:

Students design an RV32IMCX compatible CPU and run on FPGA in real-time. They also have to generate GDS files form open-source Openlane software. I was a referee for this competition and seen numerous great designs from the teams. These students, mostly go to PhD for further studies on computer architecture or find jobs in digital design tech firms.

My answer for the question, is it worth to design a RISC-V core from scratch is yes, but for educational purposes. Of course, you can still design a RISC-V core and sell it as an IP, but you have to verify it and at some point show people that it is silicon-proof to remove their hesitations.

I never designed a RISC-V core, but now I am eager to design one. I plan to design the core step-by-step, using VHDL as HDL, and aim to run the core in an FPGA board that I have, such as NEXYS A7, just for educational purposes. I will start with basics and a very simple implementation, RV32I, with no extensions, running in a single clock cycle. Then, I will improve the design with pipelining, adding extensions whenever I find time in the future. I will also record videos and publish in my YouTube channel (videos are in Turkish language). I plan to post several times for telling the details of the design.


Mehmet Burak AYKENAR

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