In the previous post, I was able to harden a RISC-V based SoC in Openlane. There were 3 methods to harden the chip according to Efabless documentation and I utilized the first method, which was hardening the macros first, then integrating all the macros in the top module by instantiating them, while there must be […]
Etiket: cpu
RISC-V Based SoC Design with Open-Source Openlane IC Design Tool
This is the second post for the series of open-source IC design flow. The first post talked about how to use open-source tools, namely Openlane to harden a RISC-V CPU core, in which we generated GDS outputs of the CPU core. The famous PicoRV32 RISC-V core is chosen for this purpose. You can find the […]
Open-Source IC Design Flow for an Open-Source RISC-V Core
I can say I am more of an RTL design engineer. I had a lot of experience in RTL design deployed in FPGA systems before gaining interest in IC design. In FPGA, or now also in SoC (Processing System [PS] + Programmable Logic [PL]) you write your RTL code in one of the HDLs, namely […]
Where to Start to Design a RISC-V CPU Core?
In my latest post, I tried to answer the question of is it worth to design a RISC-V core from scratch? The answer was yes for educational and learning purposes in my opinion. So, when someone wants to design a CPU, what is first to do and where to look at? Let’s find out together. […]
Is it Worth to Design a RISC-V Core from Scratch?
I don’t think there is anyone who never heard about RISC-V in the year of 2023, who works in the area of embedded systems or digital design and verification. If you never heard about it, please look at RISCV international webpage: https://riscv.org/ RISC-V is a royalty-free, open-standard instruction set architecture (ISA). Well, if you never […]