This is the first post on this subject: Open Source ASIC Design. I am interested in ASIC design recently. For years (>10) I designed digital circuits with VHDL. At the beginning of this year (2022), I started working in Yongatek Microelectronics company, located in Istanbul and Ankara in Turkey. Here WE {I adapted quickly and embraced the new company easilly and new Yongatek is “WE” 🙂 } design digital circuits also like my old company but this time the output circuit will work both on FPGAs and ASICs.
By the way you can learn more about Yongatek Microelectronics from this webpage:
I am new to ASIC concept, for years I designed with VHDL for AMD (formerly XILINX), INTEL (formerly ALTERA), MICROCHIP (formerly MICROSEMI, formerly ACTEL), these names are really mess nowadays 🙂 Now I started learning ASIC design flow, which is similar to FPGA design flow but back-end process is very very different. Also for front-end design there are also considerations, such as in SRAM based FPGAs you don’t care FF initialization, while in flash based FPGAs or ASIC you really need to think about reset signal !
In this post series, I will use Verilog-2005 for HDL. This will be a bit more difficult than using VHDL for me since it was years ago I was using Verilog. However, it will be a good practice for me also. By the way, you can ask why not SystemVerilog? Well, the OpenLane project, which I will talk about in detail in future, uses Yosys open source synthesizer, which only accepts Verilog-2005. You can learn more about OpenLane and Yosys from links below, but today I will use Xilinx Vivado for synthesis:
https://github.com/The-OpenROAD-Project/OpenLane
https://github.com/YosysHQ/yosys
In a digital design flow, aim for FPGA or ASIC, synthesis is usually the first step with a tool requirement. Before synthesis, of course you need to think about the architecture, I/O, HDL language etc. and then design your circuit with one of the HDLs (Verilog, VHDL, SystemVerilog) or even C/C++ with HLS tools, or Scala-based Chisel etc. Below is a N-bit up counter Verilog code with load and enable capabilities:
`timescale 1ns / 1ps
module counter
#(
parameter N = 4
)
(
input clk,
input arst_n,
input en_i,
input load_i,
input [N-1:0] load_val_i ,
output reg [N-1:0] counter_o
//output [N-1:0] counter_o
);
////////////////////////////////////////////////////////////////////////////////
// METHOD #1
////////////////////////////////////////////////////////////////////////////////
/*
reg [N-1:0] counter;
always @(posedge clk or negedge arst_n) begin
if (~arst_n) begin
counter <= 0;
end
else begin
if (load_i) begin
counter <= load_val_i;
end
else if (en_i) begin
counter <= counter + 1;
end
end
end
assign counter_o = counter;
*/
////////////////////////////////////////////////////////////////////////////////
// METHOD #2
////////////////////////////////////////////////////////////////////////////////
always @(posedge clk or negedge arst_n) begin
if (~arst_n) begin
counter_o <= 0;
end
else begin
if (load_i) begin
counter_o <= load_val_i;
end
else if (en_i) begin
counter_o <= counter_o + 1;
end
end
end
endmoduleYou can notice in the code that I tried 2 methods: First is defining output signal “counter_o” as wire (which is default type) and second is as reg. Both give same synthesis result so no problem.
After we designed our circuit, now we need to synthesis it. In this post, I will use Xilinx Vivado 2019.1 version. However, using Yosys and OpenLane flow is the ultimate object. I started this post series with Vivado because it is what I am familiar with. Also Vivado results will be a good base for comparison between Yosys synthesis results. So, in Vivado I just clicked “Run Synthesis” and the tool finished within seconds with no errors. Project summary section shows that 5 LUTs and 4 FFs are utilized for this design.
I opened the “Synthesized Design” window layout and then “schematic”:
The resolution is not so good but the important point is the elements that are utilized and their numbers. In Vivado, there is a “Netlist” window, co-tabbed with “Sources”. When you click it, it has “Nets” and “Leaf Cells” for this counter design:
When you click on a net, such as “p_0_in” it is highlighted in the “Schematics” window:
Nets are (green colored) connections between “Leaf Cells”. Well, cells are “yellow” blocks. Let’s analyze these leaf cells. In the image below, 4 FDCE cells are selected in the “Netlist” window and they are highlighted in the “Schematics” window. Well FDCE means “Primitive: D Flip-Flop with Clock Enable and Asynchronous Clear” according to Xilinx library document.
You can also right click a cell primitive and click “Go to Source” and the code part is opened in the editor:
Therefore, Vivado gives a good way to track nets and cells in the code and schematics.
Up to now, we understand that “Netlist” is actually the “cells” or “primitives”, and the “nets” which are connections between cells. Vivado gives us a good, graphical based Netlist view. However, there should be a “text-based” definition also. Well, we can export netlist file in Verilog or EDIF format in Vivado by clicking File -> Export -> Export Netlist while of course “Synthesized Design” is opened. I exported these two files in the root of the Vivado project folder for this Counter module:
Now, let’s look at “vivado_synthesis.v” file:
// Copyright 1986-2019 Xilinx, Inc. All Rights Reserved.
// --------------------------------------------------------------------------------
// Tool Version: Vivado v.2019.1 (win64) Build 2552052 Fri May 24 14:49:42 MDT 2019
// Date : Sun May 22 23:07:27 2022
// Host : DESKTOP-TSVKIOU running 64-bit major release (build 9200)
// Command : write_verilog C:/Users/ayken/OneDrive/Documents/FPGA_youtube/VivadoProjects/vivado_synthesis.v
// Design : counter
// Purpose : This is a Verilog netlist of the current design or from a specific cell of the design. The output is an
// IEEE 1364-2001 compliant Verilog HDL file that contains netlist information obtained from the input
// design files.
// Device : xc7z020clg484-1
// --------------------------------------------------------------------------------
`timescale 1 ps / 1 ps
(* N = "4" *)
(* STRUCTURAL_NETLIST = "yes" *)
module counter
(clk,
arst_n,
en_i,
load_i,
load_val_i,
counter_o);
input clk;
input arst_n;
input en_i;
input load_i;
input [3:0]load_val_i;
output [3:0]counter_o;
wire arst_n;
wire arst_n_IBUF;
wire clk;
wire clk_IBUF;
wire clk_IBUF_BUFG;
wire [3:0]counter_o;
wire \counter_o[3]_i_1_n_0 ;
wire \counter_o[3]_i_3_n_0 ;
wire [3:0]counter_o_OBUF;
wire en_i;
wire en_i_IBUF;
wire load_i;
wire load_i_IBUF;
wire [3:0]load_val_i;
wire [3:0]load_val_i_IBUF;
wire [3:0]p_0_in;
IBUF arst_n_IBUF_inst
(.I(arst_n),
.O(arst_n_IBUF));
BUFG clk_IBUF_BUFG_inst
(.I(clk_IBUF),
.O(clk_IBUF_BUFG));
IBUF clk_IBUF_inst
(.I(clk),
.O(clk_IBUF));
(* SOFT_HLUTNM = "soft_lutpair0" *)
LUT3 #(
.INIT(8'h8B))
\counter_o[0]_i_1
(.I0(load_val_i_IBUF[0]),
.I1(load_i_IBUF),
.I2(counter_o_OBUF[0]),
.O(p_0_in[0]));
(* SOFT_HLUTNM = "soft_lutpair0" *)
LUT4 #(
.INIT(16'h8BB8))
\counter_o[1]_i_1
(.I0(load_val_i_IBUF[1]),
.I1(load_i_IBUF),
.I2(counter_o_OBUF[0]),
.I3(counter_o_OBUF[1]),
.O(p_0_in[1]));
LUT5 #(
.INIT(32'h8BBBB888))
\counter_o[2]_i_1
(.I0(load_val_i_IBUF[2]),
.I1(load_i_IBUF),
.I2(counter_o_OBUF[0]),
.I3(counter_o_OBUF[1]),
.I4(counter_o_OBUF[2]),
.O(p_0_in[2]));
LUT2 #(
.INIT(4'hE))
\counter_o[3]_i_1
(.I0(en_i_IBUF),
.I1(load_i_IBUF),
.O(\counter_o[3]_i_1_n_0 ));
LUT6 #(
.INIT(64'h8BBBBBBBB8888888))
\counter_o[3]_i_2
(.I0(load_val_i_IBUF[3]),
.I1(load_i_IBUF),
.I2(counter_o_OBUF[1]),
.I3(counter_o_OBUF[0]),
.I4(counter_o_OBUF[2]),
.I5(counter_o_OBUF[3]),
.O(p_0_in[3]));
LUT1 #(
.INIT(2'h1))
\counter_o[3]_i_3
(.I0(arst_n_IBUF),
.O(\counter_o[3]_i_3_n_0 ));
OBUF \counter_o_OBUF[0]_inst
(.I(counter_o_OBUF[0]),
.O(counter_o[0]));
OBUF \counter_o_OBUF[1]_inst
(.I(counter_o_OBUF[1]),
.O(counter_o[1]));
OBUF \counter_o_OBUF[2]_inst
(.I(counter_o_OBUF[2]),
.O(counter_o[2]));
OBUF \counter_o_OBUF[3]_inst
(.I(counter_o_OBUF[3]),
.O(counter_o[3]));
FDCE #(
.INIT(1'b0))
\counter_o_reg[0]
(.C(clk_IBUF_BUFG),
.CE(\counter_o[3]_i_1_n_0 ),
.CLR(\counter_o[3]_i_3_n_0 ),
.D(p_0_in[0]),
.Q(counter_o_OBUF[0]));
FDCE #(
.INIT(1'b0))
\counter_o_reg[1]
(.C(clk_IBUF_BUFG),
.CE(\counter_o[3]_i_1_n_0 ),
.CLR(\counter_o[3]_i_3_n_0 ),
.D(p_0_in[1]),
.Q(counter_o_OBUF[1]));
FDCE #(
.INIT(1'b0))
\counter_o_reg[2]
(.C(clk_IBUF_BUFG),
.CE(\counter_o[3]_i_1_n_0 ),
.CLR(\counter_o[3]_i_3_n_0 ),
.D(p_0_in[2]),
.Q(counter_o_OBUF[2]));
FDCE #(
.INIT(1'b0))
\counter_o_reg[3]
(.C(clk_IBUF_BUFG),
.CE(\counter_o[3]_i_1_n_0 ),
.CLR(\counter_o[3]_i_3_n_0 ),
.D(p_0_in[3]),
.Q(counter_o_OBUF[3]));
IBUF en_i_IBUF_inst
(.I(en_i),
.O(en_i_IBUF));
IBUF load_i_IBUF_inst
(.I(load_i),
.O(load_i_IBUF));
IBUF \load_val_i_IBUF[0]_inst
(.I(load_val_i[0]),
.O(load_val_i_IBUF[0]));
IBUF \load_val_i_IBUF[1]_inst
(.I(load_val_i[1]),
.O(load_val_i_IBUF[1]));
IBUF \load_val_i_IBUF[2]_inst
(.I(load_val_i[2]),
.O(load_val_i_IBUF[2]));
IBUF \load_val_i_IBUF[3]_inst
(.I(load_val_i[3]),
.O(load_val_i_IBUF[3]));
endmodule
Let’s look at “vivado_synthesis.edn” file:
(edif counter
(edifversion 2 0 0)
(edifLevel 0)
(keywordmap (keywordlevel 0))
(status
(written
(timeStamp 2022 05 22 23 07 27)
(program "Vivado" (version "2019.1"))
(comment "Built on 'Fri May 24 14:49:42 MDT 2019'")
(comment "Built by 'xbuild'")
)
)
(Library hdi_primitives
(edifLevel 0)
(technology (numberDefinition ))
(cell IBUF (celltype GENERIC)
(view netlist (viewtype NETLIST)
(interface
(port O (direction OUTPUT))
(port I (direction INPUT))
)
)
)
(cell BUFG (celltype GENERIC)
(view netlist (viewtype NETLIST)
(interface
(port O (direction OUTPUT))
(port I (direction INPUT))
)
)
)
(cell LUT3 (celltype GENERIC)
(view netlist (viewtype NETLIST)
(interface
(port O (direction OUTPUT))
(port I0 (direction INPUT))
(port I1 (direction INPUT))
(port I2 (direction INPUT))
)
)
)
(cell LUT4 (celltype GENERIC)
(view netlist (viewtype NETLIST)
(interface
(port O (direction OUTPUT))
(port I0 (direction INPUT))
(port I1 (direction INPUT))
(port I2 (direction INPUT))
(port I3 (direction INPUT))
)
)
)
(cell LUT5 (celltype GENERIC)
(view netlist (viewtype NETLIST)
(interface
(port O (direction OUTPUT))
(port I0 (direction INPUT))
(port I1 (direction INPUT))
(port I2 (direction INPUT))
(port I3 (direction INPUT))
(port I4 (direction INPUT))
)
)
)
(cell LUT2 (celltype GENERIC)
(view netlist (viewtype NETLIST)
(interface
(port O (direction OUTPUT))
(port I0 (direction INPUT))
(port I1 (direction INPUT))
)
)
)
(cell LUT6 (celltype GENERIC)
(view netlist (viewtype NETLIST)
(interface
(port O (direction OUTPUT))
(port I0 (direction INPUT))
(port I1 (direction INPUT))
(port I2 (direction INPUT))
(port I3 (direction INPUT))
(port I4 (direction INPUT))
(port I5 (direction INPUT))
)
)
)
(cell LUT1 (celltype GENERIC)
(view netlist (viewtype NETLIST)
(interface
(port O (direction OUTPUT))
(port I0 (direction INPUT))
)
)
)
(cell OBUF (celltype GENERIC)
(view netlist (viewtype NETLIST)
(interface
(port O (direction OUTPUT))
(port I (direction INPUT))
)
)
)
(cell FDCE (celltype GENERIC)
(view netlist (viewtype NETLIST)
(interface
(port Q (direction OUTPUT))
(port C (direction INPUT))
(port CE (direction INPUT))
(port CLR (direction INPUT))
(port D (direction INPUT))
)
)
)
(cell INV (celltype GENERIC)
(view netlist (viewtype NETLIST)
(interface
(port I (direction INPUT))
(port O (direction OUTPUT))
)
)
)
)
(Library work
(edifLevel 0)
(technology (numberDefinition ))
(cell counter (celltype GENERIC)
(view counter (viewtype NETLIST)
(interface
(port arst_n (direction INPUT))
(port clk (direction INPUT))
(port en_i (direction INPUT))
(port load_i (direction INPUT))
(port (array (rename counter_o "counter_o[3:0]") 4) (direction OUTPUT))
(port (array (rename load_val_i "load_val_i[3:0]") 4) (direction INPUT))
)
(contents
(instance arst_n_IBUF_inst (viewref netlist (cellref IBUF (libraryref hdi_primitives))))
(instance clk_IBUF_BUFG_inst (viewref netlist (cellref BUFG (libraryref hdi_primitives))))
(instance clk_IBUF_inst (viewref netlist (cellref IBUF (libraryref hdi_primitives))))
(instance (rename counter_o_0__i_1 "counter_o[0]_i_1") (viewref netlist (cellref LUT3 (libraryref hdi_primitives)))
(property INIT (string "8'h8B"))
(property SOFT_HLUTNM (string "soft_lutpair0"))
)
(instance (rename counter_o_1__i_1 "counter_o[1]_i_1") (viewref netlist (cellref LUT4 (libraryref hdi_primitives)))
(property INIT (string "16'h8BB8"))
(property SOFT_HLUTNM (string "soft_lutpair0"))
)
(instance (rename counter_o_2__i_1 "counter_o[2]_i_1") (viewref netlist (cellref LUT5 (libraryref hdi_primitives)))
(property INIT (string "32'h8BBBB888"))
)
(instance (rename counter_o_3__i_1 "counter_o[3]_i_1") (viewref netlist (cellref LUT2 (libraryref hdi_primitives)))
(property INIT (string "4'hE"))
)
(instance (rename counter_o_3__i_2 "counter_o[3]_i_2") (viewref netlist (cellref LUT6 (libraryref hdi_primitives)))
(property INIT (string "64'h8BBBBBBBB8888888"))
)
(instance (rename counter_o_3__i_3 "counter_o[3]_i_3") (viewref netlist (cellref LUT1 (libraryref hdi_primitives)))
(property INIT (string "2'h1"))
)
(instance (rename counter_o_OBUF_0__inst "counter_o_OBUF[0]_inst") (viewref netlist (cellref OBUF (libraryref hdi_primitives))))
(instance (rename counter_o_OBUF_1__inst "counter_o_OBUF[1]_inst") (viewref netlist (cellref OBUF (libraryref hdi_primitives))))
(instance (rename counter_o_OBUF_2__inst "counter_o_OBUF[2]_inst") (viewref netlist (cellref OBUF (libraryref hdi_primitives))))
(instance (rename counter_o_OBUF_3__inst "counter_o_OBUF[3]_inst") (viewref netlist (cellref OBUF (libraryref hdi_primitives))))
(instance (rename counter_o_reg_0_ "counter_o_reg[0]") (viewref netlist (cellref FDCE (libraryref hdi_primitives)))
(property INIT (string "1'b0"))
)
(instance (rename counter_o_reg_1_ "counter_o_reg[1]") (viewref netlist (cellref FDCE (libraryref hdi_primitives)))
(property INIT (string "1'b0"))
)
(instance (rename counter_o_reg_2_ "counter_o_reg[2]") (viewref netlist (cellref FDCE (libraryref hdi_primitives)))
(property INIT (string "1'b0"))
)
(instance (rename counter_o_reg_3_ "counter_o_reg[3]") (viewref netlist (cellref FDCE (libraryref hdi_primitives)))
(property INIT (string "1'b0"))
)
(instance en_i_IBUF_inst (viewref netlist (cellref IBUF (libraryref hdi_primitives))))
(instance load_i_IBUF_inst (viewref netlist (cellref IBUF (libraryref hdi_primitives))))
(instance (rename load_val_i_IBUF_0__inst "load_val_i_IBUF[0]_inst") (viewref netlist (cellref IBUF (libraryref hdi_primitives))))
(instance (rename load_val_i_IBUF_1__inst "load_val_i_IBUF[1]_inst") (viewref netlist (cellref IBUF (libraryref hdi_primitives))))
(instance (rename load_val_i_IBUF_2__inst "load_val_i_IBUF[2]_inst") (viewref netlist (cellref IBUF (libraryref hdi_primitives))))
(instance (rename load_val_i_IBUF_3__inst "load_val_i_IBUF[3]_inst") (viewref netlist (cellref IBUF (libraryref hdi_primitives))))
(net arst_n (joined
(portref I (instanceref arst_n_IBUF_inst))
(portref arst_n)
)
)
(net arst_n_IBUF (joined
(portref I0 (instanceref counter_o_3__i_3))
(portref O (instanceref arst_n_IBUF_inst))
)
)
(net clk (joined
(portref I (instanceref clk_IBUF_inst))
(portref clk)
)
)
(net clk_IBUF (joined
(portref I (instanceref clk_IBUF_BUFG_inst))
(portref O (instanceref clk_IBUF_inst))
)
)
(net clk_IBUF_BUFG (joined
(portref C (instanceref counter_o_reg_0_))
(portref C (instanceref counter_o_reg_1_))
(portref C (instanceref counter_o_reg_2_))
(portref C (instanceref counter_o_reg_3_))
(portref O (instanceref clk_IBUF_BUFG_inst))
)
)
(net (rename counter_o_0_ "counter_o[0]") (joined
(portref O (instanceref counter_o_OBUF_0__inst))
(portref (member counter_o 3))
)
)
(net (rename counter_o_1_ "counter_o[1]") (joined
(portref O (instanceref counter_o_OBUF_1__inst))
(portref (member counter_o 2))
)
)
(net (rename counter_o_2_ "counter_o[2]") (joined
(portref O (instanceref counter_o_OBUF_2__inst))
(portref (member counter_o 1))
)
)
(net (rename counter_o_3_ "counter_o[3]") (joined
(portref O (instanceref counter_o_OBUF_3__inst))
(portref (member counter_o 0))
)
)
(net (rename counter_o_3__i_1_n_0 "counter_o[3]_i_1_n_0") (joined
(portref CE (instanceref counter_o_reg_0_))
(portref CE (instanceref counter_o_reg_1_))
(portref CE (instanceref counter_o_reg_2_))
(portref CE (instanceref counter_o_reg_3_))
(portref O (instanceref counter_o_3__i_1))
)
)
(net (rename counter_o_3__i_3_n_0 "counter_o[3]_i_3_n_0") (joined
(portref CLR (instanceref counter_o_reg_0_))
(portref CLR (instanceref counter_o_reg_1_))
(portref CLR (instanceref counter_o_reg_2_))
(portref CLR (instanceref counter_o_reg_3_))
(portref O (instanceref counter_o_3__i_3))
)
)
(net (rename counter_o_OBUF_0_ "counter_o_OBUF[0]") (joined
(portref I (instanceref counter_o_OBUF_0__inst))
(portref I2 (instanceref counter_o_0__i_1))
(portref I2 (instanceref counter_o_1__i_1))
(portref I2 (instanceref counter_o_2__i_1))
(portref I3 (instanceref counter_o_3__i_2))
(portref Q (instanceref counter_o_reg_0_))
)
)
(net (rename counter_o_OBUF_1_ "counter_o_OBUF[1]") (joined
(portref I (instanceref counter_o_OBUF_1__inst))
(portref I2 (instanceref counter_o_3__i_2))
(portref I3 (instanceref counter_o_1__i_1))
(portref I3 (instanceref counter_o_2__i_1))
(portref Q (instanceref counter_o_reg_1_))
)
)
(net (rename counter_o_OBUF_2_ "counter_o_OBUF[2]") (joined
(portref I (instanceref counter_o_OBUF_2__inst))
(portref I4 (instanceref counter_o_2__i_1))
(portref I4 (instanceref counter_o_3__i_2))
(portref Q (instanceref counter_o_reg_2_))
)
)
(net (rename counter_o_OBUF_3_ "counter_o_OBUF[3]") (joined
(portref I (instanceref counter_o_OBUF_3__inst))
(portref I5 (instanceref counter_o_3__i_2))
(portref Q (instanceref counter_o_reg_3_))
)
)
(net en_i (joined
(portref I (instanceref en_i_IBUF_inst))
(portref en_i)
)
)
(net en_i_IBUF (joined
(portref I0 (instanceref counter_o_3__i_1))
(portref O (instanceref en_i_IBUF_inst))
)
)
(net load_i (joined
(portref I (instanceref load_i_IBUF_inst))
(portref load_i)
)
)
(net load_i_IBUF (joined
(portref I1 (instanceref counter_o_0__i_1))
(portref I1 (instanceref counter_o_1__i_1))
(portref I1 (instanceref counter_o_2__i_1))
(portref I1 (instanceref counter_o_3__i_1))
(portref I1 (instanceref counter_o_3__i_2))
(portref O (instanceref load_i_IBUF_inst))
)
)
(net (rename load_val_i_0_ "load_val_i[0]") (joined
(portref I (instanceref load_val_i_IBUF_0__inst))
(portref (member load_val_i 3))
)
)
(net (rename load_val_i_1_ "load_val_i[1]") (joined
(portref I (instanceref load_val_i_IBUF_1__inst))
(portref (member load_val_i 2))
)
)
(net (rename load_val_i_2_ "load_val_i[2]") (joined
(portref I (instanceref load_val_i_IBUF_2__inst))
(portref (member load_val_i 1))
)
)
(net (rename load_val_i_3_ "load_val_i[3]") (joined
(portref I (instanceref load_val_i_IBUF_3__inst))
(portref (member load_val_i 0))
)
)
(net (rename load_val_i_IBUF_0_ "load_val_i_IBUF[0]") (joined
(portref I0 (instanceref counter_o_0__i_1))
(portref O (instanceref load_val_i_IBUF_0__inst))
)
)
(net (rename load_val_i_IBUF_1_ "load_val_i_IBUF[1]") (joined
(portref I0 (instanceref counter_o_1__i_1))
(portref O (instanceref load_val_i_IBUF_1__inst))
)
)
(net (rename load_val_i_IBUF_2_ "load_val_i_IBUF[2]") (joined
(portref I0 (instanceref counter_o_2__i_1))
(portref O (instanceref load_val_i_IBUF_2__inst))
)
)
(net (rename load_val_i_IBUF_3_ "load_val_i_IBUF[3]") (joined
(portref I0 (instanceref counter_o_3__i_2))
(portref O (instanceref load_val_i_IBUF_3__inst))
)
)
(net (rename p_0_in_0_ "p_0_in[0]") (joined
(portref D (instanceref counter_o_reg_0_))
(portref O (instanceref counter_o_0__i_1))
)
)
(net (rename p_0_in_1_ "p_0_in[1]") (joined
(portref D (instanceref counter_o_reg_1_))
(portref O (instanceref counter_o_1__i_1))
)
)
(net (rename p_0_in_2_ "p_0_in[2]") (joined
(portref D (instanceref counter_o_reg_2_))
(portref O (instanceref counter_o_2__i_1))
)
)
(net (rename p_0_in_3_ "p_0_in[3]") (joined
(portref D (instanceref counter_o_reg_3_))
(portref O (instanceref counter_o_3__i_2))
)
)
)
(property N (integer 4))
)
)
)
(comment "Reference To The Cell Of Highest Level")
(design counter
(cellref counter (libraryref work))
(property XLNX_PROJ_DIR (string "C:/Users/"not-so-related"/vivado_synthesis"))
(property part (string "xc7z020clg484-1"))
)
)EDIF is a very poppular file format and used extensively in EDA tools. You can get more information from:
https://en.wikipedia.org/wiki/EDIF
I found reading Verilog-based netlist information quite easier then EDIF-based netlist information. But it is the tool, which will use netlist is important at the end of the day.
In this post, I shortly talked about synthesis process in a digital design flow and showed an example synthesis output, which is actually called “netlist” using Xilinx Vivado. Next time, I will take same N-bit Verilog counter example and use Yosys to synthesis and create netlist.
Regards,
Mehmet Burak AYKENAR
You can connect me via LinledIn: Just sent me an invitation
https://tr.linkedin.com/in/mehmet-burak-aykenar-73326419a
Great! I will follow up the series
This is a great post! Thank you very much!