In my latest post, I talked about AXI-Stream protocol and showed a running design on Zedboard utilizing AXI-Stream FIFO and ILA: https://www.mehmetburakaykenar.com/what-is-axi-stream-protocol-axi-stream-fifo-tutorial-with-vivado-and-vitis-running-on-zynq-zedboard/377/ Today, I will show how to create a custom AXI-Stream peripheral in Vivado with VHDL. The use case is an arithmetic co-processor, where the arithmetic operation of the co-processor will be selected between […]
Etiket: vivado
XILINX ZYNQ AXI Central DMA (CDMA) On-Chip Memory (OCM), DDR3 RAM and PL Block RAM Data Transfer Performances
It has been a long time that I posted on my webpage related to Digital Design and SoC concepts. My last post was related to evaluating data transfer rates between OCM, DDR3 RAM and PL Block RAM by utilizing PS DMA of Processing System of the Zynq SoC. Please visit the related post for details: […]
XILINX ZYNQ PS DMA | On-Chip Memory (OCM), DDR3 RAM and PL BRAM Data Transfer Performances
It has been a long time that I posted on my webpage related to Digital Design and SoC concepts. This post will be related to Zynq Processing System (PS) DMA usage example and performance analysis on data transfer between DDR3 RAM, OCM and PL Block RAM. I will provide both PL and PS designs and […]
FPGA Synthesis | Xilinx Spartan-3E/6 and 7-Series Library Analysis
In my previous, actually first post about ASIC design with open source tools, I talked about the first automation step, which is synthesis and its output, which is a netlist: https://www.mehmetburakaykenar.com/first-step-to-asic-design-synthesis-netlist-verilog-counter-example-on-vivado/254/ We saw that an N-bit Verilog counter code is synthesized into logic cells and nets connecting them. File formats for this information in Vivado […]
First Step to ASIC Design: Synthesis & Netlist | Verilog Counter Example on Vivado
This is the first post on this subject: Open Source ASIC Design. I am interested in ASIC design recently. For years (>10) I designed digital circuits with VHDL. At the beginning of this year (2022), I started working in Yongatek Microelectronics company, located in Istanbul and Ankara in Turkey. Here WE {I adapted quickly and […]
AXI4-FULL AXI4-LITE and UART INTERFACE SIMULATION in MODELSIM with UVVM LIBRARY
In my last post, I showed how to design a custom AXI4 IP in Vivado, having an AXI4-Full, AXI4-Lite and a UART interface: https://www.mehmetburakaykenar.com/how-to-create-an-axi4-full-custom-ip-with-axi4-lite-and-uart-interfaces-in-vivado/192/ Now I will show how to verify this IP using UVVM library. In my previous posts, I showed how to verify AXI4-Lite and UART interfaces with UVVM BFM (bus functional model) […]
HOW TO CREATE an AXI4-FULL CUSTOM IP with AXI4-LITE and UART INTERFACES in VIVADO
In this post, I will show how to create a custom IP in Vivado, which has an AXI4-Lite interface, an AXI4-Full interface and a UART interface. Long time ago, when I first met with Zynq and a Microblaze SOM, I started learning how to generate a custom AXI4-Lite IP from Mr. Adam Taylor’s Microzed Chronicles blog. Now it is my time to contribute to the digital design community by showing AXI4-Full IP generation and an example code utilizing a UART interface.
CLOCK DOMAIN CROSSING (CDC) – USING FIFOs – HIGH SPEED UART TRANSCIEVER EXAMPLE
Timing in digital systems was a very challenging subject when I first saw it. Metastability, synchronization, MTBF (mean time between failure), setup & hold times, clock skew, clock jitter are some of the concepts about timing in digital systems. When you work in a single clock domain, where a single clock drives all flip-flops, timing […]
AN INTRODUCTORY MODELSIM TUTORIAL for VIVADO & XILINX USERS
Digital design is a hot topic, it was, and it will be in near future according to some surveys if you google it. If you want to be a digital design engineer or if you are now and want to see job opportunities, you will see different job descriptions. One difference is, if you are […]