In the previous post, I was able to harden a RISC-V based SoC in Openlane. There were 3 methods to harden the chip according to Efabless documentation and I utilized the first method, which was hardening the macros first, then integrating all the macros in the top module by instantiating them, while there must be […]
Yazar: Burak Aykenar

RISC-V Based SoC Design with Open-Source Openlane IC Design Tool
This is the second post for the series of open-source IC design flow. The first post talked about how to use open-source tools, namely Openlane to harden a RISC-V CPU core, in which we generated GDS outputs of the CPU core. The famous PicoRV32 RISC-V core is chosen for this purpose. You can find the […]

Open-Source IC Design Flow for an Open-Source RISC-V Core
I can say I am more of an RTL design engineer. I had a lot of experience in RTL design deployed in FPGA systems before gaining interest in IC design. In FPGA, or now also in SoC (Processing System [PS] + Programmable Logic [PL]) you write your RTL code in one of the HDLs, namely […]

Where to Start to Design a RISC-V CPU Core?
In my latest post, I tried to answer the question of is it worth to design a RISC-V core from scratch? The answer was yes for educational and learning purposes in my opinion. So, when someone wants to design a CPU, what is first to do and where to look at? Let’s find out together. […]

Is it Worth to Design a RISC-V Core from Scratch?
I don’t think there is anyone who never heard about RISC-V in the year of 2023, who works in the area of embedded systems or digital design and verification. If you never heard about it, please look at RISCV international webpage: https://riscv.org/ RISC-V is a royalty-free, open-standard instruction set architecture (ISA). Well, if you never […]

Verification of a Custom AXI-Stream IP with VHDL using UVVM Library
In my latest post, I showed how to create a custom AXI-Stream IP in Vivado. This basic IP was an arithmetic coprocessor accelerator, performs addition, subtraction or multiplication according to the configuration: https://www.mehmetburakaykenar.com/creating-custom-axi-stream-ip-tutorial-with-vivado/397/ In that post, I just showed how to create the IP in Vivado and write the RTL code, but did not verify […]

Creating Custom AXI-Stream IP Tutorial with Vivado
In my latest post, I talked about AXI-Stream protocol and showed a running design on Zedboard utilizing AXI-Stream FIFO and ILA: https://www.mehmetburakaykenar.com/what-is-axi-stream-protocol-axi-stream-fifo-tutorial-with-vivado-and-vitis-running-on-zynq-zedboard/377/ Today, I will show how to create a custom AXI-Stream peripheral in Vivado with VHDL. The use case is an arithmetic co-processor, where the arithmetic operation of the co-processor will be selected between […]
SEÇİMİNİ YAP: EVRENİ YÜCE BİR YARATICI YARATTI vs EVREN RASTLANTISAL OLARAK OLUŞTU
2023 yılı Ağustos ayında Ankara’da ikamet eden birisinin şu anda en büyük problemlerinden bir tanesi sıcaklık! Gerçekten de Ağustos ayı inanılmaz sıcak geçiyor, birkaç gündür üst üste 40 derece civarında hava sıcaklığı var. Gece uyumak mümkün değil, gündüz dışarı çıkmak inanılmaz kötü bir tecrübe. Muhtemelen bu yılın, ya da geçmiş herhangi bir yılın Ocak ayında […]

What is AXI-Stream protocol? AXI-Stream FIFO Tutorial with Vivado and Vitis, running on ZYNQ, ZEDBOARD
So far in my blogs I utilized Zynq PS DMA and AXI CDMA IPs to move data between DDR RAM, on-chip ram (OCM) and PL Block RAM (BRAM). I have designed Vivado HW and Vitis SW parts and showed latency results for these two scenarios, which you can find at the links all the details: […]

XILINX ZYNQ AXI Central DMA (CDMA) On-Chip Memory (OCM), DDR3 RAM and PL Block RAM Data Transfer Performances
It has been a long time that I posted on my webpage related to Digital Design and SoC concepts. My last post was related to evaluating data transfer rates between OCM, DDR3 RAM and PL Block RAM by utilizing PS DMA of Processing System of the Zynq SoC. Please visit the related post for details: […]