I don’t want to get into the discussion of which is better for HDL programming VHDL or Verilog. I just want to compare some language constructs of the two. The reason I am writing this post is just to remember me and who reads it what language construct, block is equivalent to other, a kind of cheat sheet or etc.
Etiket: FPGA
SPI (SERIAL PERIPHERAL INTERFACE) SIMULATION in MODELSIM with UVVM LIBRARY
Now it is time to verify one of my designs which is a driver of ADXL362 Accelerometer IC having an SPI interface with UVVM’s spi_bfm_pkg VHDL package.
AXI4-FULL AXI4-LITE and UART INTERFACE SIMULATION in MODELSIM with UVVM LIBRARY
In my last post, I showed how to design a custom AXI4 IP in Vivado, having an AXI4-Full, AXI4-Lite and a UART interface: https://www.mehmetburakaykenar.com/how-to-create-an-axi4-full-custom-ip-with-axi4-lite-and-uart-interfaces-in-vivado/192/ Now I will show how to verify this IP using UVVM library. In my previous posts, I showed how to verify AXI4-Lite and UART interfaces with UVVM BFM (bus functional model) […]
HOW TO CREATE an AXI4-FULL CUSTOM IP with AXI4-LITE and UART INTERFACES in VIVADO
In this post, I will show how to create a custom IP in Vivado, which has an AXI4-Lite interface, an AXI4-Full interface and a UART interface. Long time ago, when I first met with Zynq and a Microblaze SOM, I started learning how to generate a custom AXI4-Lite IP from Mr. Adam Taylor’s Microzed Chronicles blog. Now it is my time to contribute to the digital design community by showing AXI4-Full IP generation and an example code utilizing a UART interface.
VERIFICATION of A CUSTOM AXI4 LITE IP USING UVVM
If you are using or plan to use Xilinx Zynq (or any other SoC), most probably you will encounter creating your own IP modules and the poppular way to connect your IP to Processing System is via AXI4 protocol.
KALMAN FILTER IMPLEMENTATION on ZYNQ PS (ARM CORTEX-A9) and LATENCY MEASUREMENTS
This post is about Kalman filter implementation with C++ using Eigen library and running it on Xilinx Zynq SoC PS part. Beware! Latency measurements will show the reader some good info!
CLOCK DOMAIN CROSSING (CDC) – USING FIFOs – HIGH SPEED UART TRANSCIEVER EXAMPLE
Timing in digital systems was a very challenging subject when I first saw it. Metastability, synchronization, MTBF (mean time between failure), setup & hold times, clock skew, clock jitter are some of the concepts about timing in digital systems. When you work in a single clock domain, where a single clock drives all flip-flops, timing […]
INTEGER DIVISION in FPGAs with VHDL APPROACH
If you google “addition in vhdl”, “subtraction in vhdl” or “multiply in vhdl” of “… in fpga”, you get tons of results, tutorials and example codes sometimes with detailed utilization and timing analysis with them. But have you ever considered and searched for “division in fpga/vhdl/verilog” etc? Well I did! First you need to choose […]
VHDL ile FPGA PROGRAMLAMA
VHDL ile FPGA PROGRAMLAMA – Ders1: FPGA Programlamaya Başlamak İsteyenlere Bilgiler VHDL ile FPGA PROGRAMLAMA – Ders2: FPGA Sektörü İş olanakları Kariyer Seçenekleri VHDL ile FPGA PROGRAMLAMA: SON DERS | DERSLERİN KISA ÖZETLERİ | TEŞEKKÜR ve GELECEK ÇALIŞMALAR VHDL ile FPGA PROGRAMLAMA – Ders3: Xilinx Vivado ile Proje Oluşturma Synthesis ve Implementation VHDL ile FPGA […]