In the previous post, I was able to harden a RISC-V based SoC in Openlane. There were 3 methods to harden the chip according to Efabless documentation and I utilized the first method, which was hardening the macros first, then integrating all the macros in the top module by instantiating them, while there must be […]
Etiket: Verilog
XILINX ZYNQ AXI Central DMA (CDMA) On-Chip Memory (OCM), DDR3 RAM and PL Block RAM Data Transfer Performances
It has been a long time that I posted on my webpage related to Digital Design and SoC concepts. My last post was related to evaluating data transfer rates between OCM, DDR3 RAM and PL Block RAM by utilizing PS DMA of Processing System of the Zynq SoC. Please visit the related post for details: […]
First Step to ASIC Design: Synthesis & Netlist | Verilog Counter Example on Vivado
This is the first post on this subject: Open Source ASIC Design. I am interested in ASIC design recently. For years (>10) I designed digital circuits with VHDL. At the beginning of this year (2022), I started working in Yongatek Microelectronics company, located in Istanbul and Ankara in Turkey. Here WE {I adapted quickly and […]
VHDL vs VERILOG – NOT WHICH IS BETTER COMPARISON !!!
I don’t want to get into the discussion of which is better for HDL programming VHDL or Verilog. I just want to compare some language constructs of the two. The reason I am writing this post is just to remember me and who reads it what language construct, block is equivalent to other, a kind of cheat sheet or etc.