So far in my blogs I utilized Zynq PS DMA and AXI CDMA IPs to move data between DDR RAM, on-chip ram (OCM) and PL Block RAM (BRAM). I have designed Vivado HW and Vitis SW parts and showed latency results for these two scenarios, which you can find at the links all the details: […]
Etiket: fifo
VERIFICATION of the HIGH SPEED UART TRANSCIEVER with FIFO CDCs USING UVVM
In my last post, I utilized FIFOs for CDC synchronization for a high speed UART transciever system. To remeber, there were a UART receiver and a UART transmitter, which run at 250 MHz and the internal logic runs at 100 MHz. There are FIFOs between two clock domains, where ona side of the FIFO runs […]
CLOCK DOMAIN CROSSING (CDC) – USING FIFOs – HIGH SPEED UART TRANSCIEVER EXAMPLE
Timing in digital systems was a very challenging subject when I first saw it. Metastability, synchronization, MTBF (mean time between failure), setup & hold times, clock skew, clock jitter are some of the concepts about timing in digital systems. When you work in a single clock domain, where a single clock drives all flip-flops, timing […]