Now it is time to verify one of my designs which is a driver of ADXL362 Accelerometer IC having an SPI interface with UVVM’s spi_bfm_pkg VHDL package.
Yazar: Burak Aykenar
AXI4-FULL AXI4-LITE and UART INTERFACE SIMULATION in MODELSIM with UVVM LIBRARY
In my last post, I showed how to design a custom AXI4 IP in Vivado, having an AXI4-Full, AXI4-Lite and a UART interface: https://www.mehmetburakaykenar.com/how-to-create-an-axi4-full-custom-ip-with-axi4-lite-and-uart-interfaces-in-vivado/192/ Now I will show how to verify this IP using UVVM library. In my previous posts, I showed how to verify AXI4-Lite and UART interfaces with UVVM BFM (bus functional model) […]
HOW TO CREATE an AXI4-FULL CUSTOM IP with AXI4-LITE and UART INTERFACES in VIVADO
In this post, I will show how to create a custom IP in Vivado, which has an AXI4-Lite interface, an AXI4-Full interface and a UART interface. Long time ago, when I first met with Zynq and a Microblaze SOM, I started learning how to generate a custom AXI4-Lite IP from Mr. Adam Taylor’s Microzed Chronicles blog. Now it is my time to contribute to the digital design community by showing AXI4-Full IP generation and an example code utilizing a UART interface.
VERIFICATION of A CUSTOM AXI4 LITE IP USING UVVM
If you are using or plan to use Xilinx Zynq (or any other SoC), most probably you will encounter creating your own IP modules and the poppular way to connect your IP to Processing System is via AXI4 protocol.
KALMAN FILTER IMPLEMENTATION on ZYNQ PS (ARM CORTEX-A9) and LATENCY MEASUREMENTS
This post is about Kalman filter implementation with C++ using Eigen library and running it on Xilinx Zynq SoC PS part. Beware! Latency measurements will show the reader some good info!
KALMAN FILTER IMPLEMENTATION in C++ WITH EIGEN LIBRARY in VISUAL STUDIO
Well this is the first time I am posting about a subject other than VHDL, FPGA or verification. Now it is time for SOFTWARE and ALGORITHMS !!!
VERIFICATION of the HIGH SPEED UART TRANSCIEVER with FIFO CDCs USING UVVM
In my last post, I utilized FIFOs for CDC synchronization for a high speed UART transciever system. To remeber, there were a UART receiver and a UART transmitter, which run at 250 MHz and the internal logic runs at 100 MHz. There are FIFOs between two clock domains, where ona side of the FIFO runs […]
CLOCK DOMAIN CROSSING (CDC) – USING FIFOs – HIGH SPEED UART TRANSCIEVER EXAMPLE
Timing in digital systems was a very challenging subject when I first saw it. Metastability, synchronization, MTBF (mean time between failure), setup & hold times, clock skew, clock jitter are some of the concepts about timing in digital systems. When you work in a single clock domain, where a single clock drives all flip-flops, timing […]
A UVVM EXAMPLE UART TRANSMITTER TESTBENCH SIMULATION on MODELSIM
In the last blog, I showed how to use Modelsim from Vivado and how to compile Xilinx libraries for Modelsim. https://www.mehmetburakaykenar.com/an-introductory-modelsim-tutorial-for-vivado-xilinx-users/116/ This time I will compile UVVM (Universal VHDL Verification Methodology) library for Modelsim and use util and BFM packages of UVVM to simulate uart_tx.vhd module. You can download uart_tx.vhd file from my github page: […]
AN INTRODUCTORY MODELSIM TUTORIAL for VIVADO & XILINX USERS
Digital design is a hot topic, it was, and it will be in near future according to some surveys if you google it. If you want to be a digital design engineer or if you are now and want to see job opportunities, you will see different job descriptions. One difference is, if you are […]