In my latest post, I showed how to create a custom AXI-Stream IP in Vivado. This basic IP was an arithmetic coprocessor accelerator, performs addition, subtraction or multiplication according to the configuration: https://www.mehmetburakaykenar.com/creating-custom-axi-stream-ip-tutorial-with-vivado/397/ In that post, I just showed how to create the IP in Vivado and write the RTL code, but did not verify […]
Etiket: Verification
SPI (SERIAL PERIPHERAL INTERFACE) SIMULATION in MODELSIM with UVVM LIBRARY
Now it is time to verify one of my designs which is a driver of ADXL362 Accelerometer IC having an SPI interface with UVVM’s spi_bfm_pkg VHDL package.
AXI4-FULL AXI4-LITE and UART INTERFACE SIMULATION in MODELSIM with UVVM LIBRARY
In my last post, I showed how to design a custom AXI4 IP in Vivado, having an AXI4-Full, AXI4-Lite and a UART interface: https://www.mehmetburakaykenar.com/how-to-create-an-axi4-full-custom-ip-with-axi4-lite-and-uart-interfaces-in-vivado/192/ Now I will show how to verify this IP using UVVM library. In my previous posts, I showed how to verify AXI4-Lite and UART interfaces with UVVM BFM (bus functional model) […]
VERIFICATION of A CUSTOM AXI4 LITE IP USING UVVM
If you are using or plan to use Xilinx Zynq (or any other SoC), most probably you will encounter creating your own IP modules and the poppular way to connect your IP to Processing System is via AXI4 protocol.
VERIFICATION of the HIGH SPEED UART TRANSCIEVER with FIFO CDCs USING UVVM
In my last post, I utilized FIFOs for CDC synchronization for a high speed UART transciever system. To remeber, there were a UART receiver and a UART transmitter, which run at 250 MHz and the internal logic runs at 100 MHz. There are FIFOs between two clock domains, where ona side of the FIFO runs […]
A UVVM EXAMPLE UART TRANSMITTER TESTBENCH SIMULATION on MODELSIM
In the last blog, I showed how to use Modelsim from Vivado and how to compile Xilinx libraries for Modelsim. https://www.mehmetburakaykenar.com/an-introductory-modelsim-tutorial-for-vivado-xilinx-users/116/ This time I will compile UVVM (Universal VHDL Verification Methodology) library for Modelsim and use util and BFM packages of UVVM to simulate uart_tx.vhd module. You can download uart_tx.vhd file from my github page: […]