In my last post, I showed how to design a custom AXI4 IP in Vivado, having an AXI4-Full, AXI4-Lite and a UART interface: https://www.mehmetburakaykenar.com/how-to-create-an-axi4-full-custom-ip-with-axi4-lite-and-uart-interfaces-in-vivado/192/ Now I will show how to verify this IP using UVVM library. In my previous posts, I showed how to verify AXI4-Lite and UART interfaces with UVVM BFM (bus functional model) […]
Etiket: uart
HOW TO CREATE an AXI4-FULL CUSTOM IP with AXI4-LITE and UART INTERFACES in VIVADO
In this post, I will show how to create a custom IP in Vivado, which has an AXI4-Lite interface, an AXI4-Full interface and a UART interface. Long time ago, when I first met with Zynq and a Microblaze SOM, I started learning how to generate a custom AXI4-Lite IP from Mr. Adam Taylor’s Microzed Chronicles blog. Now it is my time to contribute to the digital design community by showing AXI4-Full IP generation and an example code utilizing a UART interface.
A UVVM EXAMPLE UART TRANSMITTER TESTBENCH SIMULATION on MODELSIM
In the last blog, I showed how to use Modelsim from Vivado and how to compile Xilinx libraries for Modelsim. https://www.mehmetburakaykenar.com/an-introductory-modelsim-tutorial-for-vivado-xilinx-users/116/ This time I will compile UVVM (Universal VHDL Verification Methodology) library for Modelsim and use util and BFM packages of UVVM to simulate uart_tx.vhd module. You can download uart_tx.vhd file from my github page: […]