In the last blog, I showed how to use Modelsim from Vivado and how to compile Xilinx libraries for Modelsim. https://www.mehmetburakaykenar.com/an-introductory-modelsim-tutorial-for-vivado-xilinx-users/116/ This time I will compile UVVM (Universal VHDL Verification Methodology) library for Modelsim and use util and BFM packages of UVVM to simulate uart_tx.vhd module. You can download uart_tx.vhd file from my github page: […]