If you are using or plan to use Xilinx Zynq (or any other SoC), most probably you will encounter creating your own IP modules and the poppular way to connect your IP to Processing System is via AXI4 protocol.
Ay: Aralık 2021
KALMAN FILTER IMPLEMENTATION on ZYNQ PS (ARM CORTEX-A9) and LATENCY MEASUREMENTS
This post is about Kalman filter implementation with C++ using Eigen library and running it on Xilinx Zynq SoC PS part. Beware! Latency measurements will show the reader some good info!
KALMAN FILTER IMPLEMENTATION in C++ WITH EIGEN LIBRARY in VISUAL STUDIO
Well this is the first time I am posting about a subject other than VHDL, FPGA or verification. Now it is time for SOFTWARE and ALGORITHMS !!!
VERIFICATION of the HIGH SPEED UART TRANSCIEVER with FIFO CDCs USING UVVM
In my last post, I utilized FIFOs for CDC synchronization for a high speed UART transciever system. To remeber, there were a UART receiver and a UART transmitter, which run at 250 MHz and the internal logic runs at 100 MHz. There are FIFOs between two clock domains, where ona side of the FIFO runs […]
CLOCK DOMAIN CROSSING (CDC) – USING FIFOs – HIGH SPEED UART TRANSCIEVER EXAMPLE
Timing in digital systems was a very challenging subject when I first saw it. Metastability, synchronization, MTBF (mean time between failure), setup & hold times, clock skew, clock jitter are some of the concepts about timing in digital systems. When you work in a single clock domain, where a single clock drives all flip-flops, timing […]